High-level specification languages for designing an application specific integrated circuit (ASIC) have made it possible for a chip designer to design an ASIC at a functional level rather than having to generate detailed schematic diagrams. Once the functional level description has been generated, software tools can be used to synthesize the functional level description to a circuit level implementation.
In addition to enabling design of an ASIC at a functional level, software tools also are available for simulating the ASIC at both the functional level and at the circuit level. Often it is necessary to perform simulations at both levels to ensure correct functionality and freedom from timing errors.
A complex ASIC design may require simulation using large amounts of test data, sometimes referred to herein as test vectors, to exercise all features of the ASIC and to ensure that all the components of the ASIC have been tested using the full ranges of buses, registers, and memories. Although "testbench" code can be used to generate test vectors for testing the functional level ASIC design, the process of generating such test vectors is labor-intensive. Also, test vectors written for simulation at the functional level may require changes to work when the synthesized circuit must be simulated.
For example, certain classes of ASIC applications such as digital beamforming for an ultrasound or radar system present a particular challenge for test vector generation. Specifically, digital beamforming ASICs are very complex and have many different operating modes. In addition, no simple test such as a Fourier Transform can be performed on the output data to ensure that the ASIC design functions correctly. Therefore, a variety of test vectors must be generated to exercise each ASIC functional mode, and human judgment must be used to examine the simulation output to decide if the desired functionality has been implemented correctly.
The above described process for generating test vectors for testing ASICs is a tedious and error-prone process. It would be desirable to provide a tool for more automated generation of such test vectors, including test vectors for complex ASICs such as digital beamforming ASICs. It also would be desirable for such tool to generate test vectors for both the functional level design and the circuit level design, and for such tool to compare the results from both levels of testing to ensure correct ASIC functionality and freedom from timing errors.